The proliferation of integrated circuits has placed increasing demands on the design of digital systems and microprocessors included in many devices, components, and architectures. The number of digital systems that include microprocessors continues to steadily increase and is driven by a wide array of products and systems. Added functionalities may be implemented in integrated circuits in order to execute additional tasks or to effectuate more sophisticated operations in their respective applications or environments.
In the context of microprocessors, present generation embedded systems have stringent requirements on accuracy, performance, and power consumption. Many embedded systems employ sophisticated algorithms for communications, image processing, video processing etc, which can be computationally intensive. Mesh or grid architectures are popular for distributing critical global signals on a chip such as clock and power/ground. The mesh architecture uses inherent redundancy created by loops to smooth out undesirable variations between signal nodes spatially distributed over the chip. These variations can be due to non-uniform switching activity in the design, within-die process variations and asymmetric distribution of circuit elements (such as flip-flops). For power/ground, mesh can help reduce voltage variations at different nodes in the network due to non-uniform switching activities.
However, one imposing problem that has limited the applicability of mesh architectures is the difficulty in analyzing them with sufficient accuracy. The main reasons are the huge number of circuit nodes needed to accurately model a fine mesh in a large design and large number of metal loops (cycles) present in the mesh structure. Accordingly, the ability to address these issues/complex operations to achieve optimal processing provides a significant challenge to system designers and component manufacturers alike.